Software:Article Title: Linking of simulators into a circuit design tool
Article Snippet: .. Note that in the example code segments presented herein, “XSim” or “xsim” refers to Vivado circuit simulation software from XILINX, Inc. # Copyright 2014 Xilinx, Inc. namespace eval::tclapp::xilinx::xsim { proc setup {args} { # Summary: initialize global vars and prepare for simulation # Argument Usage: # args: command line args passed from launch_simulation tcl task # Return Value: # true (0) if success, false (1) otherwise # initialize global variables ::tclapp::xilinx::xsim::usf_init_vars # initialize XSim simulator variables usf_xsim_init_simulation_vars # read simulation command line args and set global variables usf_xsim_setup_args $args # perform initial simulation tasks if {[usf_xsim_setup_simulation] } { return 1 } return 0 } proc compile {args} { # Summary: run the compile step for compiling the design files # Argument Usage: # args: command line args passed from launch_simulation tcl task # Return Value: # none usf_xsim_write_compile_script set proc_name [lindex [split [info level 0] “ ”] 0] set step [lindex [split $proc_name {:}] end] ::tclapp::xilinx::xsim::usf_launch_script “xsim” $step } proc elaborate {args} { # Summary: run the elaborate step for elaborating the compiled design # Argument Usage: # args: command line args passed from launch_simulation tcl task # Return Value: # none send_msg_id Vivado-XSim-003 INFO “xsim::elaborate design” usf_xsim_write_elaborate_script set proc_name [lindex [split [info level 0] “ ”] 0] set step [lindex [split $proc_name {:}] end] ::tclapp::xilinx::xsim::usf_launch_script “xsim” $step } proc simulate {args} { # Summary: run the simulate step for simulating the elaborated design # Argument Usage: # args: command line args passed from launch_simulation tcl task # Return Value: # none send_msg_id Vivado-XSim-004 INFO “xsim::simulate design” usf_xsim_write_simulate_script set proc_name [lindex [split [info level 0] “ ”] 0] set step [lindex [split $proc_name {:}] end] ::tclapp::xilinx::xsim::usf_launch_script “xsim” $step } } At block 208, fileset options are stored in response to a user command that specifies the values of the options. ..
Blocking Assay:Article Title: Linking of simulators into a circuit design tool
Article Snippet: .. Note that in the example code segments presented herein, “XSim” or “xsim” refers to Vivado circuit simulation software from XILINX, Inc. # Copyright 2014 Xilinx, Inc. namespace eval::tclapp::xilinx::xsim { proc setup {args} { # Summary: initialize global vars and prepare for simulation # Argument Usage: # args: command line args passed from launch_simulation tcl task # Return Value: # true (0) if success, false (1) otherwise # initialize global variables ::tclapp::xilinx::xsim::usf_init_vars # initialize XSim simulator variables usf_xsim_init_simulation_vars # read simulation command line args and set global variables usf_xsim_setup_args $args # perform initial simulation tasks if {[usf_xsim_setup_simulation] } { return 1 } return 0 } proc compile {args} { # Summary: run the compile step for compiling the design files # Argument Usage: # args: command line args passed from launch_simulation tcl task # Return Value: # none usf_xsim_write_compile_script set proc_name [lindex [split [info level 0] “ ”] 0] set step [lindex [split $proc_name {:}] end] ::tclapp::xilinx::xsim::usf_launch_script “xsim” $step } proc elaborate {args} { # Summary: run the elaborate step for elaborating the compiled design # Argument Usage: # args: command line args passed from launch_simulation tcl task # Return Value: # none send_msg_id Vivado-XSim-003 INFO “xsim::elaborate design” usf_xsim_write_elaborate_script set proc_name [lindex [split [info level 0] “ ”] 0] set step [lindex [split $proc_name {:}] end] ::tclapp::xilinx::xsim::usf_launch_script “xsim” $step } proc simulate {args} { # Summary: run the simulate step for simulating the elaborated design # Argument Usage: # args: command line args passed from launch_simulation tcl task # Return Value: # none send_msg_id Vivado-XSim-004 INFO “xsim::simulate design” usf_xsim_write_simulate_script set proc_name [lindex [split [info level 0] “ ”] 0] set step [lindex [split $proc_name {:}] end] ::tclapp::xilinx::xsim::usf_launch_script “xsim” $step } } At block 208, fileset options are stored in response to a user command that specifies the values of the options. ..
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